mirror of
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remove package github.com/docopt/docopt-go
This commit is contained in:
fatedier
262
vendor/github.com/klauspost/cpuid/private/cpuid.go
generated
vendored
262
vendor/github.com/klauspost/cpuid/private/cpuid.go
generated
vendored
@@ -12,146 +12,146 @@ import (
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type vendor int
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const (
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other vendor = iota
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other vendor = iota
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intel
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amd
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via
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transmeta
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nsc
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kvm // Kernel-based Virtual Machine
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msvm // Microsoft Hyper-V or Windows Virtual PC
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kvm // Kernel-based Virtual Machine
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msvm // Microsoft Hyper-V or Windows Virtual PC
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vmware
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xenhvm
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)
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const (
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cmov = 1 << iota // i686 CMOV
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nx // NX (No-Execute) bit
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amd3dnow // AMD 3DNOW
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amd3dnowext // AMD 3DNowExt
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mmx // standard MMX
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mmxext // SSE integer functions or AMD MMX ext
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sse // SSE functions
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sse2 // P4 SSE functions
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sse3 // Prescott SSE3 functions
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ssse3 // Conroe SSSE3 functions
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sse4 // Penryn SSE4.1 functions
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sse4a // AMD Barcelona microarchitecture SSE4a instructions
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sse42 // Nehalem SSE4.2 functions
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avx // AVX functions
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avx2 // AVX2 functions
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fma3 // Intel FMA 3
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fma4 // Bulldozer FMA4 functions
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xop // Bulldozer XOP functions
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f16c // Half-precision floating-point conversion
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bmi1 // Bit Manipulation Instruction Set 1
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bmi2 // Bit Manipulation Instruction Set 2
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tbm // AMD Trailing Bit Manipulation
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lzcnt // LZCNT instruction
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popcnt // POPCNT instruction
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aesni // Advanced Encryption Standard New Instructions
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clmul // Carry-less Multiplication
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htt // Hyperthreading (enabled)
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hle // Hardware Lock Elision
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rtm // Restricted Transactional Memory
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rdrand // RDRAND instruction is available
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rdseed // RDSEED instruction is available
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adx // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
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sha // Intel SHA Extensions
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avx512f // AVX-512 Foundation
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avx512dq // AVX-512 Doubleword and Quadword Instructions
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avx512ifma // AVX-512 Integer Fused Multiply-Add Instructions
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avx512pf // AVX-512 Prefetch Instructions
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avx512er // AVX-512 Exponential and Reciprocal Instructions
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avx512cd // AVX-512 Conflict Detection Instructions
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avx512bw // AVX-512 Byte and Word Instructions
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avx512vl // AVX-512 Vector Length Extensions
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avx512vbmi // AVX-512 Vector Bit Manipulation Instructions
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mpx // Intel MPX (Memory Protection Extensions)
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erms // Enhanced REP MOVSB/STOSB
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rdtscp // RDTSCP Instruction
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cx16 // CMPXCHG16B Instruction
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cmov = 1 << iota // i686 CMOV
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nx // NX (No-Execute) bit
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amd3dnow // AMD 3DNOW
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amd3dnowext // AMD 3DNowExt
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mmx // standard MMX
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mmxext // SSE integer functions or AMD MMX ext
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sse // SSE functions
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sse2 // P4 SSE functions
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sse3 // Prescott SSE3 functions
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ssse3 // Conroe SSSE3 functions
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sse4 // Penryn SSE4.1 functions
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sse4a // AMD Barcelona microarchitecture SSE4a instructions
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sse42 // Nehalem SSE4.2 functions
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avx // AVX functions
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avx2 // AVX2 functions
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fma3 // Intel FMA 3
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fma4 // Bulldozer FMA4 functions
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xop // Bulldozer XOP functions
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f16c // Half-precision floating-point conversion
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bmi1 // Bit Manipulation Instruction Set 1
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bmi2 // Bit Manipulation Instruction Set 2
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tbm // AMD Trailing Bit Manipulation
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lzcnt // LZCNT instruction
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popcnt // POPCNT instruction
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aesni // Advanced Encryption Standard New Instructions
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clmul // Carry-less Multiplication
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htt // Hyperthreading (enabled)
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hle // Hardware Lock Elision
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rtm // Restricted Transactional Memory
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rdrand // RDRAND instruction is available
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rdseed // RDSEED instruction is available
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adx // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
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sha // Intel SHA Extensions
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avx512f // AVX-512 Foundation
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avx512dq // AVX-512 Doubleword and Quadword Instructions
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avx512ifma // AVX-512 Integer Fused Multiply-Add Instructions
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avx512pf // AVX-512 Prefetch Instructions
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avx512er // AVX-512 Exponential and Reciprocal Instructions
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avx512cd // AVX-512 Conflict Detection Instructions
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avx512bw // AVX-512 Byte and Word Instructions
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avx512vl // AVX-512 Vector Length Extensions
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avx512vbmi // AVX-512 Vector Bit Manipulation Instructions
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mpx // Intel MPX (Memory Protection Extensions)
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erms // Enhanced REP MOVSB/STOSB
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rdtscp // RDTSCP Instruction
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cx16 // CMPXCHG16B Instruction
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// Performance indicators
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sse2slow // SSE2 is supported, but usually not faster
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sse3slow // SSE3 is supported, but usually not faster
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atom // Atom processor, some SSSE3 instructions are slower
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sse2slow // SSE2 is supported, but usually not faster
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sse3slow // SSE3 is supported, but usually not faster
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atom // Atom processor, some SSSE3 instructions are slower
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)
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var flagNames = map[flags]string{
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cmov: "CMOV", // i686 CMOV
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nx: "NX", // NX (No-Execute) bit
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amd3dnow: "AMD3DNOW", // AMD 3DNOW
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amd3dnowext: "AMD3DNOWEXT", // AMD 3DNowExt
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mmx: "MMX", // Standard MMX
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mmxext: "MMXEXT", // SSE integer functions or AMD MMX ext
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sse: "SSE", // SSE functions
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sse2: "SSE2", // P4 SSE2 functions
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sse3: "SSE3", // Prescott SSE3 functions
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ssse3: "SSSE3", // Conroe SSSE3 functions
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sse4: "SSE4.1", // Penryn SSE4.1 functions
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sse4a: "SSE4A", // AMD Barcelona microarchitecture SSE4a instructions
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sse42: "SSE4.2", // Nehalem SSE4.2 functions
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avx: "AVX", // AVX functions
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avx2: "AVX2", // AVX functions
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fma3: "FMA3", // Intel FMA 3
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fma4: "FMA4", // Bulldozer FMA4 functions
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xop: "XOP", // Bulldozer XOP functions
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f16c: "F16C", // Half-precision floating-point conversion
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bmi1: "BMI1", // Bit Manipulation Instruction Set 1
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bmi2: "BMI2", // Bit Manipulation Instruction Set 2
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tbm: "TBM", // AMD Trailing Bit Manipulation
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lzcnt: "LZCNT", // LZCNT instruction
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popcnt: "POPCNT", // POPCNT instruction
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aesni: "AESNI", // Advanced Encryption Standard New Instructions
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clmul: "CLMUL", // Carry-less Multiplication
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htt: "HTT", // Hyperthreading (enabled)
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hle: "HLE", // Hardware Lock Elision
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rtm: "RTM", // Restricted Transactional Memory
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rdrand: "RDRAND", // RDRAND instruction is available
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rdseed: "RDSEED", // RDSEED instruction is available
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adx: "ADX", // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
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sha: "SHA", // Intel SHA Extensions
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avx512f: "AVX512F", // AVX-512 Foundation
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avx512dq: "AVX512DQ", // AVX-512 Doubleword and Quadword Instructions
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avx512ifma: "AVX512IFMA", // AVX-512 Integer Fused Multiply-Add Instructions
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avx512pf: "AVX512PF", // AVX-512 Prefetch Instructions
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avx512er: "AVX512ER", // AVX-512 Exponential and Reciprocal Instructions
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avx512cd: "AVX512CD", // AVX-512 Conflict Detection Instructions
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avx512bw: "AVX512BW", // AVX-512 Byte and Word Instructions
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avx512vl: "AVX512VL", // AVX-512 Vector Length Extensions
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avx512vbmi: "AVX512VBMI", // AVX-512 Vector Bit Manipulation Instructions
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mpx: "MPX", // Intel MPX (Memory Protection Extensions)
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erms: "ERMS", // Enhanced REP MOVSB/STOSB
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rdtscp: "RDTSCP", // RDTSCP Instruction
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cx16: "CX16", // CMPXCHG16B Instruction
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cmov: "CMOV", // i686 CMOV
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nx: "NX", // NX (No-Execute) bit
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amd3dnow: "AMD3DNOW", // AMD 3DNOW
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amd3dnowext: "AMD3DNOWEXT", // AMD 3DNowExt
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mmx: "MMX", // Standard MMX
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mmxext: "MMXEXT", // SSE integer functions or AMD MMX ext
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sse: "SSE", // SSE functions
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sse2: "SSE2", // P4 SSE2 functions
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sse3: "SSE3", // Prescott SSE3 functions
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ssse3: "SSSE3", // Conroe SSSE3 functions
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sse4: "SSE4.1", // Penryn SSE4.1 functions
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sse4a: "SSE4A", // AMD Barcelona microarchitecture SSE4a instructions
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sse42: "SSE4.2", // Nehalem SSE4.2 functions
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avx: "AVX", // AVX functions
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avx2: "AVX2", // AVX functions
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fma3: "FMA3", // Intel FMA 3
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fma4: "FMA4", // Bulldozer FMA4 functions
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xop: "XOP", // Bulldozer XOP functions
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f16c: "F16C", // Half-precision floating-point conversion
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bmi1: "BMI1", // Bit Manipulation Instruction Set 1
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bmi2: "BMI2", // Bit Manipulation Instruction Set 2
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tbm: "TBM", // AMD Trailing Bit Manipulation
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lzcnt: "LZCNT", // LZCNT instruction
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popcnt: "POPCNT", // POPCNT instruction
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aesni: "AESNI", // Advanced Encryption Standard New Instructions
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clmul: "CLMUL", // Carry-less Multiplication
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htt: "HTT", // Hyperthreading (enabled)
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hle: "HLE", // Hardware Lock Elision
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rtm: "RTM", // Restricted Transactional Memory
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rdrand: "RDRAND", // RDRAND instruction is available
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rdseed: "RDSEED", // RDSEED instruction is available
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adx: "ADX", // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
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sha: "SHA", // Intel SHA Extensions
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avx512f: "AVX512F", // AVX-512 Foundation
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avx512dq: "AVX512DQ", // AVX-512 Doubleword and Quadword Instructions
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avx512ifma: "AVX512IFMA", // AVX-512 Integer Fused Multiply-Add Instructions
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avx512pf: "AVX512PF", // AVX-512 Prefetch Instructions
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avx512er: "AVX512ER", // AVX-512 Exponential and Reciprocal Instructions
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avx512cd: "AVX512CD", // AVX-512 Conflict Detection Instructions
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avx512bw: "AVX512BW", // AVX-512 Byte and Word Instructions
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avx512vl: "AVX512VL", // AVX-512 Vector Length Extensions
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avx512vbmi: "AVX512VBMI", // AVX-512 Vector Bit Manipulation Instructions
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mpx: "MPX", // Intel MPX (Memory Protection Extensions)
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erms: "ERMS", // Enhanced REP MOVSB/STOSB
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rdtscp: "RDTSCP", // RDTSCP Instruction
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cx16: "CX16", // CMPXCHG16B Instruction
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// Performance indicators
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sse2slow: "SSE2SLOW", // SSE2 supported, but usually not faster
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sse3slow: "SSE3SLOW", // SSE3 supported, but usually not faster
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atom: "ATOM", // Atom processor, some SSSE3 instructions are slower
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sse2slow: "SSE2SLOW", // SSE2 supported, but usually not faster
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sse3slow: "SSE3SLOW", // SSE3 supported, but usually not faster
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atom: "ATOM", // Atom processor, some SSSE3 instructions are slower
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}
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// CPUInfo contains information about the detected system CPU.
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type cpuInfo struct {
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brandname string // Brand name reported by the CPU
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vendorid vendor // Comparable CPU vendor ID
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features flags // Features of the CPU
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physicalcores int // Number of physical processor cores in your CPU. Will be 0 if undetectable.
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threadspercore int // Number of threads per physical core. Will be 1 if undetectable.
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logicalcores int // Number of physical cores times threads that can run on each core through the use of hyperthreading. Will be 0 if undetectable.
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family int // CPU family number
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model int // CPU model number
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cacheline int // Cache line size in bytes. Will be 0 if undetectable.
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cache struct {
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l1i int // L1 Instruction Cache (per core or shared). Will be -1 if undetected
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l1d int // L1 Data Cache (per core or shared). Will be -1 if undetected
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l2 int // L2 Cache (per core or shared). Will be -1 if undetected
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l3 int // L3 Instruction Cache (per core or shared). Will be -1 if undetected
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brandname string // Brand name reported by the CPU
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vendorid vendor // Comparable CPU vendor ID
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features flags // Features of the CPU
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physicalcores int // Number of physical processor cores in your CPU. Will be 0 if undetectable.
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threadspercore int // Number of threads per physical core. Will be 1 if undetectable.
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logicalcores int // Number of physical cores times threads that can run on each core through the use of hyperthreading. Will be 0 if undetectable.
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family int // CPU family number
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model int // CPU model number
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cacheline int // Cache line size in bytes. Will be 0 if undetectable.
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cache struct {
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l1i int // L1 Instruction Cache (per core or shared). Will be -1 if undetected
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l1d int // L1 Data Cache (per core or shared). Will be -1 if undetected
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l2 int // L2 Cache (per core or shared). Will be -1 if undetected
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l3 int // L3 Instruction Cache (per core or shared). Will be -1 if undetected
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}
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maxFunc uint32
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maxExFunc uint32
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maxFunc uint32
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maxExFunc uint32
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}
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var cpuid func(op uint32) (eax, ebx, ecx, edx uint32)
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@@ -638,18 +638,18 @@ func physicalCores() int {
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// Except from http://en.wikipedia.org/wiki/CPUID#EAX.3D0:_Get_vendor_ID
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var vendorMapping = map[string]vendor{
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"AMDisbetter!": amd,
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"AuthenticAMD": amd,
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"CentaurHauls": via,
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"GenuineIntel": intel,
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"TransmetaCPU": transmeta,
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"GenuineTMx86": transmeta,
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"Geode by NSC": nsc,
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"VIA VIA VIA ": via,
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"KVMKVMKVMKVM": kvm,
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"Microsoft Hv": msvm,
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"VMwareVMware": vmware,
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"XenVMMXenVMM": xenhvm,
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"AMDisbetter!": amd,
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"AuthenticAMD": amd,
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"CentaurHauls": via,
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"GenuineIntel": intel,
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"TransmetaCPU": transmeta,
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"GenuineTMx86": transmeta,
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"Geode by NSC": nsc,
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"VIA VIA VIA ": via,
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"KVMKVMKVMKVM": kvm,
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"Microsoft Hv": msvm,
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"VMwareVMware": vmware,
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"XenVMMXenVMM": xenhvm,
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}
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func vendorID() vendor {
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@@ -668,10 +668,10 @@ func cacheLine() int {
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}
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_, ebx, _, _ := cpuid(1)
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cache := (ebx & 0xff00) >> 5 // cflush size
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cache := (ebx & 0xff00) >> 5 // cflush size
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if cache == 0 && maxExtendedFunction() >= 0x80000006 {
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_, _, ecx, _ := cpuid(0x80000006)
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cache = ecx & 0xff // cacheline size
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cache = ecx & 0xff // cacheline size
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}
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// TODO: Read from Cache and TLB Information
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return int(cache)
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Reference in New Issue
Block a user